Delay fault test quality calculation apparatus, delay fault test quality calculation method, and delay fault test pattern generation apparatus

ABSTRACT

A delay fault test quality calculation apparatus for calculating delay fault test quality to be achieved by a test pattern to be applied to a semiconductor integrated circuit includes a defect distribution extraction unit, a delay fault-layout element information extraction unit, and a weighting unit. The delay fault test quality calculation apparatus further includes a delay fault test quality calculation unit which calculates the delay fault test quality on the basis of delay design information of the semiconductor integrated circuit, detection information of the test pattern to test the semiconductor integrated circuit, execution conditions of the test, a physical defect distribution extracts the defect distribution extraction unit, and a weights adds the weighting unit.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromprior Japanese Patent Application No. 2006-314221, filed Nov. 21, 2006,the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a delay fault test technique to be used for asemiconductor integrated circuit. More specifically, the presentinvention relates to a calculation apparatus for calculating delay faulttest quality, a method for calculating the quality thereof, and a delayfault test pattern generation apparatus.

2. Description of the Related Art

In recent years, a delay fault has become worse in accordance with highperformance and high frequency of a semiconductor integrated circuit(hereinafter referred to as a large scale integrated circuit [LSI]).Conventionally, in the case in which the LSI cannot operate normally ata prescribed test frequency, the cause is called a delay defect.

As to the most basic fault model corresponding to the delay fault(defect), there are a transition fault model and a path delay faultmodel. The former is the simplest delay fault model and is effective todetect a large delay fault (delay defect) inside the LSI. The transitionfault is assumed as slow-to-rise or slow-to-fall fault at an input andoutput terminal of a connection net or a basic cell inside a target LSI.The former has practical advantages that it simply comes out by a simpleexpansion of a stuck-at fault model and it may treat the delay faults ina comprehensive manner. On the contrary, the latter assumes the delayfault in each logical path in the target LSI, although it has anadvantage capable of detecting distributed delays on the logical paths,the number of the logical paths becomes huge, and also a large number ofredundant paths exist therein. Therefore, there are problems such that,in many case, applying a test pattern poses an extremely low value of afault coverage, namely the number of tested logical paths/the number ofall logical paths, and it is very hard to estimate the degree of thedelay fault test quality. Because of such a reason, in general, thetransition fault model has been widely used.

However, with respect to an LSI to be manufactured in recent fineprocess, physical defects which cause fine ((very) small) delaysincrease in number, so that a generation of a test pattern correspondingto a conventional generic transition fault model cannot sufficientlydetect a physical defect causing a fine delay fault. Accordingly, thesituation in which the delay fault is exposed after the shipment of theLSI has become worse.

Therefore, to detect the physical defect causing a fine delay fault,many proposals have been presented. A representative proposal generatesa test pattern so as to detect the physical defect causing a fine delayfault by a logical path almost the longest path as much as possible onthe basis of the transition fault model capable of detecting the defectin a comprehensive manner. However, this proposal is an effort to detectfurther many physical defects causing a fine delay fault, does notanswer a question that the delay fault test quality of the test pattern,which has been actually obtained as a result, is to which degree, sothat a suitable quality index is desired.

With respect to the estimation of the delay fault test quality, avariety of proposals have been presented. Especially, in a patentdocument 1 (e.g., Jpn. Pat. Appln. KOKAI No. 2005-257654), the proposalput together into one quality index from a comprehensive point of view.That is, in patent document 1, the proposal calculates the delay faulttest quality with high precision, based on the delay fault coverage, anddelay (timing) design information (e.g., static timing analysisinformation) of the target LSI, test timing precision (test frequency)information of a test pattern applied to the target LSI, and commondelay defect distribution information. In the case of patent document 1,there is a large advantage in that an experimental question that anoccurrence rate of delay faults is low in some products, and high inother products even with the same delay fault coverage may be explainedreasonably, and it has found a course capable of estimating an actualmarket delay fault (defect) rate level with high precision.

A patent document 2 (e.g., Jpn. Pat. Appln. KOKAI Publication No.2004-251895) proposes to estimate the delay fault test quality with highprecision by adding layout information to the delay fault.

In another point of view, as to enhancing precision of a fault model, ina non-patent document (e.g., Zhuo Li, et al., “A Circuit Level FaultModel for Resistive Opens and Bridges”, Session 11 B-1, VTS 2003,2003.), the quality improvement of generation of the delay fault test isconfirmed by modeling a resistive defect that is a main cause of thedelay fault in a circuit level.

However, patent document 1 only proposes an indirect method, such as amethod for directly obtaining through a test element group (TEG)measurement (hard in reality) and a method for estimating by evaluatinga large number of samples of target products (obtaining optimumsolutions of the target products is delayed, and hard to develop theestimation result for other products), in a manner how to obtain a delayfault distribution that is the start point of a measure (metric) of thedelay fault test quality. While patent document 1 assumes one kind ofthe delay defect distribution, (as disclosed in this patentspecification), in an actual product the delay defect distribution ofeach delay fault differ much from that of the other, patent document 1does not clearly describe a method for reasonably obtaining the way thatwhich distributions should be employed, and then, it has notsufficiently disclosed the point to estimate the delay fault testquality of may products with high precision. In other words, althoughpatent document 1 specifies that a direct distribution of delay defects(faults) is extracted from the common TEG, and the delay fault testquality is calculated on the basis of the extracted distribution, thereis some doubt whether or not the delay defect distribution extractedfrom the common TEG can be applied as delay defect distributions ofindividual products as it is. The delay defect itself is expressed byabnormalities of further direct and common physical parameters(resistance [R] and capacitance [C]), and the parameters deeply dependon the unique layout of the product.

In patent document 2, since the weight to be added to the delay faulthas not accurately responded to layout element information, there isevery possibility that an appropriate delay defect distribution cannotbe obtained. Although non-patent document 1 takes resistive faults intoaccount, it does not reach the idea of combining the resistive faultswith the physical defect distributions of the individual layoutelements.

BRIEF SUMMARY OF THE INVENTION

According to a first aspect of the present invention, there is provideda delay fault test quality calculation apparatus for calculating delayfault test quality to be achieved by a test pattern to be applied to asemiconductor integrated circuit comprises:

a defect distribution extraction unit which extracts a physical defectdistribution of resistance or current related to layout elements or acombination of the layout elements composing the semiconductorintegrated circuit;

a delay fault-layout element information extraction unit which extractsthe layout elements or the combination of the layout elements inside thesemiconductor integrated circuit as delay fault-layout elementinformation by associating the layout elements or the combinationthereof with delay faults to be assumed inside the semiconductorintegrated circuit;

a weighting unit which adds weights of the layout elements or thecombination of the layout elements on the basis of the delayfault-layout element information for each delay fault; and

a delay fault test quality calculation unit which calculates the delayfault test quality on the basis of delay design information of thesemiconductor integrated circuit, detection information of the testpattern to test the semiconductor integrated circuit, executionconditions of the test, the physical defect distribution, and theweights.

According to a second aspect of the present invention, there is provideda delay fault test quality calculation method for calculating delayfault test quality to be achieved by a test pattern to be applied to asemiconductor integrated circuit comprises:

extracting a physical defect distribution of resistance or currentrelated to layout elements or a combination of the layout elementscomposing the semiconductor integrated circuit;

extracting the layout elements or the combination of the layout elementsinside the semiconductor integrated circuit as delay fault-layoutelement information by associating the layout elements or thecombination thereof with delay faults to be assumed inside thesemiconductor integrated circuit;

adding weights of the layout elements or the combination of the layoutelements on the basis of the delay fault-layout element information foreach delay fault; and

calculating the delay fault test quality on the basis of delay designinformation of the semiconductor integrated circuit, detectioninformation of the test pattern to test the semiconductor integratedcircuit, execution conditions of the test, the physical defectdistribution, and the weights.

According to a third aspect of the present invention, there is provideda delay fault test pattern generation apparatus for generating a delayfault test pattern comprises:

a defect distribution extraction unit which extracts a physical defectdistribution of resistance or current related to layout elements or acombination of the layout elements composing the semiconductorintegrated circuit;

a delay fault-layout element information extraction unit which extractsthe layout elements or the combination of the layout elements inside thesemiconductor integrated circuit as delay fault-layout elementinformation by associating the layout elements or the combinationthereof with delay faults to be assumed inside the semiconductorintegrated circuit;

a weighting unit which adds weights of the layout elements or thecombination of the layout elements on the basis of the delayfault-layout element information for each delay fault;

a test pattern generation unit which preferentially generates a testpattern for not-detected faults with heavy weights on the basis ofweights of faults to which the weights are added by the weighting unit;and

a delay fault test quality calculation unit which calculates the delayfault test quality on the basis of delay design information of thesemiconductor integrated circuit, detection information of the testpattern to test the semiconductor integrated circuit, executionconditions of the test, the physical defect distribution, and theweights.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 is a preferred view illustrating a delay defect distribution to acertain fault together with a test pattern applying result to an LSI;

FIG. 2 is a preferred view schematically illustrating an aspect of adistribution of target layout elements on an interconnect;

FIG. 3A is a preferred view illustrating a relationship among abnormaldelay values and load capacities, FIG. 3B is a preferred viewillustrating an RC net, FIG. 3C is a preferred view illustrating anotherrelationship among the abnormal delay values and the load capacities,and FIG. 3D is a preferred view illustrating another relationship amongthe abnormal delay values and the load capacities;

FIG. 4 is a preferred view collectively illustrating a flow until adelay defect distribution averaged in RC nets or faults in the LSI;

FIG. 5 is a preferred view illustrating an execution flow in accordancewith the first embodiment of the invention;

FIG. 6 is a preferred view illustrating an execution flow in accordancewith the second embodiment of the invention;

FIG. 7 is a preferred view illustrating a method of acquiring detectioninformation for each VIA (target layout element) on interconnectsections;

FIG. 8 is a preferred view illustrating an execution flow in accordancewith the third embodiment of the invention;

FIG. 9 is a preferred view illustrating an execution flow in accordancewith the fourth embodiment of the fourth embodiment; and

FIG. 10 is a preferred circuit view illustrating a configuration exampleof a two-input AND gate.

DETAILED DESCRIPTION OF THE INVENTION

Embodiment of the invention will be described with reference to theaccompanying drawings. It should be noted that the drawings areschematic ones and the dimension ratios shown therein are different fromthe actual ones. The dimensions vary from therein are different from theactual ones. The dimensions vary drawing to drawing and so do the ratiosof dimensions. The following embodiments are directed to a device and amethod for embodying the technical concept of the present invention andthe technical concept does not specify the material, shape, structure orconfiguration of components of the present invention. Various changesand modifications can be made to the technical concept without departingfrom the scope of the claimed invention.

As mentioned above, while patent document 1 assumes one kind of thedelay defect distribution for all faults, in an actual product the delaydefect distribution of each delay fault differ from that of the other.Further, the delay distributions of a product may differ from those ofanother product. Therefore, there is still some doubt as to theapplication of the delay defect distribution extracted from the commonTEG as it is as the delay defect distribution of the individualproducts. The delay defect should be originally represented by thecombination (association) of abnormalities of the further direct andcommon physical parameters of basic elements constituting circuits ofthe individual products, especially R of (or the current [1/R] flowingthrough) an element, and the physical parameter (mainly, C) of thecircuit elements to be affected by the abnormalities; and especially,the latter deeply depends on the unique layouts of the products.Further, the delay defect distribution deeply depends on the effectivenumber and amounts of basic elements to be associated with (capable ofsuffering abnormalities) each delay fault to be assumed inside theproduct, and this fact depend heavily on the unique layout of theproducts, and this deal defect distribution deeply depends on thelayouts unique to the products. Conversely, without extractingresistance (R) abnormality distribution caused by the physical defect tobe targeted to the resistive open fault (defect) of a VIA/metalinterconnect that is the most basic element from the common TEG,extracting effective number and quantity (length) of the VIA/metalinterconnect to be associated with the delay fault of the product, andappropriately combining the extracted resistance (R) distribution andthe extracted effective number and quantity (length), the estimation ofthe delay fault test quality in patent document 1 may not reach the testquality of the delay fault caused by the objected physical defect withhigh accuracy.

The embodiment described hereinafter will provide a delay fault testquality calculation apparatus, its calculation method and delay faulttest pattern generation apparatus which are actualized by obtainingphysical defect (failure) distributions of a various layout elementsshared with at least specific process and manufacturing line and a delaydefect distributions at each LSI on the basis of the information uniqueto each LSI including the layout information, and through test patternsaimed to detect the delay defect applied to each of the LSIs.

Thereby, for example, the test quality of the delay fault caused fromthe targeted physical defect may be calculated with high precision.

Some of the embodiments of the invention will be described withreference to the drawings. For this description, common parts will bedesignated common reference symbols over all Figures.

First Embodiment

At first, a concept of a measure (metric) of delay fault test qualitydescribed in patent document 1 will be explained.

FIG. 1 shows a delay defect distribution (occurrence frequencydistribution) F(D) to a certain failure i together with a result of testpattern applying to an LSI. Tmgn is, for example, a delay valueaccompanied by an “activatable” propagation path obtained by a timinganalysis, and Tdet is a delay value accompanied by a propagation pathcan be activated by an actual test. D<Tmgn indicates a redundant regionwhich is hard to be activated by any test pattern, and the region ofD≧Tmgn is the region which should be tested essentially. Now, the delayin the region of Tmgn≦D<Tdet cannot be detected even when the delayfault(defect) actually occurs, therefore, the delay defect occurrencerate in the region of Tmgn≦D<Tdet contributes to the delay fault testquality (delay defect rate) of the fault. In the patent document No. 1,the method for obtaining the measure of the delay fault test qualityassumes the same delay defect distribution F(D) to all the faults tocalculate the defect rates in the region of Tmgn≦D<Tdet, sums the defectrates, and then, calculates the measure of the delay fault test qualitybased on the test pattern applied to the LSI.

In a generic LSI, since interconnect capacities vary for each individuallogical net, the delay defect distribution F(D) is generally expressedas F(i,j)(D) (here, i is a logical net name, j is an input or outputterminal name of a logical gate to be connected to a logical net).However, from a statistics view point, there is some possibility ofenabling a suitable averaged value (distribution) to be defined, patentdocument 1 describes on the premise of the definition, but it does notdescribe a clear procedure. The first embodiment will bring this pointinto focus. More specifically, the procedure obtains the physical defectdistribution expressed by resistances or currents of a target layoutelement (e.g., a via [hereinafter referred to as a VIA] of a minimumsize) from the TEG, etc., on the other hand, the procedure extracts thedistribution of the target layout elements from the layout informationof the LSI in a form capable of associating the distribution thereofwith the delay defects, obtains the delay defect distributions caused bythe physical defect distributions of the target layout elements of therespective faults by using an appropriately modeled (simplified)“resistance into delay conversion formula”, and acquires an averageddelay defect distribution simplified through appropriate statisticalaveraging from the delay defect distributions. Hereinafter, theprocedure will be described step by step.

At first, the resistive physical defect distribution f(R) may beobtained, for example, in a process evaluation TEG, by checking a defectdistribution at an overlapped section of a section extremely exceeding adispersion range of normal resistance values (e.g., resistance value notsmaller than average+3σ=Ro) and a section before becoming suitable to betreated as an open fault (e.g., resistance value of not larger than R1=1MΩ) (∫₀ ^(∞)f(R)dR=1 and ∫_(R0) ^(R1)f(R)dR=p(<<1)).

The defect occurrence rate (frequency) may be obtained by dividing thedetected number of defects by “a quantity of target layout elements (thenumber of VIAs, interconnect length) included in one unit of TEG (e.g.,a chain of VIAs [and interconnects])×the measured total number ofunits”.

However, generally, since it is needed for obtaining such a defectdistribution to perform a large quantity of measurements, and since itmay be considered to be that the shape of the distribution and thedefect occurrence rate vary due to an improvement of a yield of theproducts, it is considered to be that continuously obtaining thehigh-reliability physical defect distributions is achieved without heavyburden by setting a simple TEG for evaluation in an empty region of alayout of each product, by measuring at the same time of shipment testsof the products, and by accumulating the measurement results.

The association of the distribution of the target layout elements to thedelay faults from the layout information of the LSI will be described byreferring to FIG. 2. FIG. 2 illustrates schematically an aspect of adistribution of target layout elements (VIAs) on interconnect. Thesignal in the LSI is propagated by the activation of the logical pathsfrom an external input terminal P1 (plurality is available) of the LSIto an external output terminal PO (plurality is available). Now, alogical net (net) i exiting on the logical path is taken into account.An output terminal of a NOR gate and input terminals of three logicalgates (three fan-outs) are connected to the net (i), and transitionfaults (i, 1), (i, 2) and (i, 3) are assumed thereto, respectively. Nowa physical path path_1 (thick full line) as a propagation path of adelay fault to a fault (i, 2) is taken into account, and a resistiveopen defect of a resistive defect occurrence source (VIAk) is taken intoaccount, the affection of the failure appears at the fault (i, 2) [and,(i, 1)]. Therefore, the affection of the resistive defect (physicaldefect) of a layout element referred to as the VIAk appears at a delayfault existing at an end edge of the physical path path_1. That is, itis appropriate to add the weight of the target layout element (VIA) tothe delay fault (input fault) assumed at the input terminal of eachlogical gate [the same applies to the fault (i, 3)]. As for delay defectcaused by incide cell defect, it appears at the output terminal of theNOR gate. It is possible to assign the defect to the delay fault at theoutput terminal of the NOR gate, or to those (i,1), (i,2), (i,3) at theinput terminals of the three logic gates, depending on modeling ofweighted delay faults.

As to the link between the foregoing delay fault and the layout elementinformation, a delay fault-layout element information link file may bedefined. The following will describe the example of the link file.

(Example of Delay Fault-Layout Element Information Link File)

net N_<net ID>:<net name>, <interconnect length on net>,    <number ofVIAs on net>(<single>, <double>), <number of terminal>;    (definitionpart of layout element (simple form)) F_<fault ID>: <equivalent faultinformation>, (slack related information),    P_<pin ID>,<cellname>/<terminal name>,<in|out>;    . Path_<path ID>: P_<pin ID>, (layoutelements on Path),    P_<pin ID>;.    . endnet

(Complements)

-   -   equivalent fault information: Representative fault=rep,        equivalent fault=eq<fault ID of representative fault>    -   <fault ID>: <fault type> serial number, corresponding to each        <instance name>/<terminal name>.    -   fault type: SR=slow_to_rise SF=slow_to_fall    -   slack related information: <minimum detection slack><clock at a        start point><clock at an end point><minimum slack><clock at a        start point><clock at an end point>    -   <clock at start point>, <clock at end point> are simply        represented by 1, 2, 3, . . . .    -   Definition sections of layout elements are granted serial        numbers in the whole of the target net for each element.        -   inside parentheses is output in the case of full format    -   format definition name (ID): information to be described;    -   Metal section W<layer1>_<serial number>:<length>, (<coordinate        of start point>), (<coordinate of end point>)        -   (metal section is a linear section sectioned by VIAs)    -   VIA V<layer1><layer2>_<serial number>: (<center coordinate>);        (layer1<layer2)

Output Example

-   net-   N_(—)5805838:top.dmac.dma_datablk.s182.N403, 13.60, 5(2,3), 3;-   M2_(—)5805846: 1.60,;-   M2_(—)5805848: 1.90,;-   M3_(—)5805850: 3.70,;-   M3_(—)5805851: 6.40,;-   V23_(—)5805839:;-   V23_(—)5805840:;-   V23_(—)5805841:;-   V23_(—)5805842:;-   V12_(—)5805844:;-   F_SR159283: eqSR33928, TD, 259, 1, 1, 236, 1, 1, P_(—)159283,    CND2X1/A, in;-   F_SF159283: eqSF33928, TD, 283, 1, 1, 241, 1, 1, P_(—)159283,    CND2X1/A, in;-   F_SR159284: eqSF53392, TD, 219, 1, 1, 205, 1, 1, P_(—)159284,    CND3X1/B in;-   F_SF159284: eqSR53392, TD, 230, 1, 1, 219, 1, 1, P_(—)159284,    CND3X1/B, in;-   F_SR72847: rep, TD, 285, 1, 1, 251, 1, 1, P 72847, CIvX1/z, out-   F_SF72847: rep, TD, 278, 1, 1, 243, 1, 1, P_(—)72847, CIVX1/z, out    -   Path_(—)5805852:P_(—)72847, V23_(—)5805841, M3_(—)5805850,        V23_(—)58 05842,    -   M2_(—)5805846, V23_(—)5805839, M3_(—)5805851, V23_(—)5805840,        P_(—)15 9283;    -   Path_(—)5805853:P_(—)72847, V23_(—)5805841, M3_(—)5805850,        V23_(—)58 05842,    -   M2_(—)5805846, M2_(—)5805848, P_(—)159284;    -   endnet

In the above link file, lines of F_SR, . . . , F_SF, . . . , show eachdelay fault, respectively, and show the corresponding terminal names,Path_ . . . enumerates layout element (here, VIA/interconnect element)on a physical path up to each input terminal, and enables clearlygrasping the association among the delay faults and the layout elementinformation. The slack indicates a degree of time to spare of timing,the slack related information provides Tmgn and Tdet of each delayfault.

In the conversion formula of ‘resistance into delay’, generallydescribes the VIA as follows:

D(i,k _({j}) ,R)=C(i,k _({j}))×fLOC(i,k _({j}))×R (VIAk on net (i))

[{j}=(partial) aggregate of faults assumed at a connection destinationbasic cell input terminals of net (i)]

fLOC is detailed position information of the inside of the LSI logicalnet of each VIA. The VIAk on the net (i) has a possibility of existingon a plurality of physical paths. That is, since there is somepossibility of having an influence on some faults assumed at the inputterminals of a connection destination basic cells of the net (i)corresponding to the end point of each physical path, the VIAk isexpressed as k_({j}). Using the conversion formula by simplifying it inappropriate modeling makes it possible to obtain the delay defectdistribution through a minimum necessary calculation amount. Forinstance, in the simplest modeling, a method for executing the detailedsimulations on some nets, set C(i,k_({j})) to C(i) (“a total loadcapacitance of net (i)”=sum of total interconnect capacitance on net (i)and input and output capacitance of basic cells, connected to net (i)[in a large scale LSI, influence is apt to become small]), and forreplacing the fLOC to an appropriate fixed value n is a possibleapproach.

FIG. 3A shows this example (in the case of interconnect without anybranch). The lateral axis indicates load capacities from a start pointto an end point and from a certain position (a VIA) to an end point, oneach net of the LSI. The load capacitance is almost in proportion to theposition on the physical path. On the contrary, the longitudinal axisindicates abnormal delays caused by VIA defects (resistance R) whichhave occurred at each position (if lateral axis is viewed from theoutput end, the aforementioned conversion formula is made). On thelateral axis, the VIAs existing on the physical path are indicated withwhite squares, and the corresponding-abnormal delays are indicated withwhite circles (correspondence relationships are indicated with dashedlines).

Here, it is estimated that the distribution of the VIAs is almost evenon the physical path, an abnormal delay value nRC (indicated as a whitelozenge) at an averaged position between the start point and the endpoint of the physical path is set as an averaged abnormal delay value,and this delay value, namely the conversion formula of ‘resistance intodelay’ D=nRC (resistance into delay conversion formula to be used fornet (i)) may be applied for all the VIAs on the net (i). If the RC netin a lump formula is assumed (refer to FIG. 3B), the delay risen fromthe resistive failure of the VIA positioned at an input end of the net(i) is ‘RC’, and ‘n=½’ is established. However, actually (if precisionof approximation is further enhanced), the delay becomes smaller thatthe given value in many case, so that it is needed to execute asufficient circuit simulation in response to necessary accuracy and toselect a value of n approximately.

As shown in FIG. 3C, there is some possibility of deviation of thedistribution of the VIAs on some physical path. Therefore, an averagedabnormal delay value (resistance into delay conversion formula) may beobtained after accurately reflecting relative distances of each VIA(this obtaining equivalents to obtain a resistance into delay conversionformula of net by using fLOC for each individual VIA). Thus, an averagedresistance into delay conversion formula is expressed as ‘D=mRC’, and mbecomes a substantially smaller value than n.

Further, if there is any branch in interconnect, a plurality of physicalpaths exist, in response to this fact, a plurality of resistance intodelay conversion formulas exist as shown in FIG. 3D, the VIAs on theside closer to the interconnect input than the branch (VIAs on aplurality of physical paths) gets a delay value by any conversionformula in accordance with the fact that which of physical paths is usedfor the propagation of the signal (if a plurality of physical paths areused for the simultaneous propagation, the conversion formula whichposes the largest delay is applied). Therefore, the averaged resistanceinto delay conversion formula of the net including the branch may beacquired, for example, by obtaining the averaged abnormal delay value ofindividual VIAs with taking the frequency of the activation of eachphysical path (resistance into delay conversion formula correspondingthereto) into account.

Thus, including a generic net with any branch, while it is achieved toobtain resistance into delay conversion formulas by net to which acertain extent of high accuracy is expected and to acquire a delaydefect distribution expression to be applied to the whole of the belowmentioned LSI, it is also necessary to extract further detailed layoutinformation in comparison to the simplest method. The aforementioneddelay fault-layout information link file includes such information(however, it is needed to add a simple tool enabling calculating aterminal capacitance and an interconnect load capacitance from aterminal name and an interconnect length of a basic cell). As understoodfrom the given description, the averaged resistance into delayconversion formula may be obtained in response not to each net but toeach physical path in the net (i) (or, fault j assumed at a tip end ofeach physical path), and may obtain the delay defect distribution on thebasis of the ‘resistance into delay conversion formula to be used forfaults i, j’ (mentioned later).

While the given example has been described the resistance into delayconversion formula accompanied by the resistive defect of the VIA, inthe case of taking the resistive defect of the interconnect instead ofthe VIA into consideration, the interconnect may be divided intoappropriate size to be extracted (specification of above mentioned delayfault-layout information link may be expanded), and may be processed ina like manner for the above described VIA.

As given above, the some of acquisition methods of the resistance intodelay conversion formula have been described from a simple one to anaccuracy-improved one. Other than this, (in a delay defect distributionand delay fault test quality), to achieve necessary precision, modelingand approximate methods in a various levels are possible approaches;however these approaches are included in the range of the firstembodiment.

Next to this, the acquisition method of the resistance-delay conversionformula generates delay defect distribution F(i)(D) of the individualnets or delay defect distribution F(i,j)(D) of the individual faults onthe LSI from the resistance defect distribution f(R) of the VIA by useof the individual net or resistance into delay conversion formulaobtained in the given manner. Basically, the following conversionformulas may be used, respectively.

F(i)(D)×dD=NVIA(i)×f(R)×dD(i)/dR×dR

F(i,j)(D)×dD=NVIA(i,j)×f(R)×dD(i,j)/dR×dR

In the given conversion formulas, NVIA(i), D(i) are each of the numbersof VIAs included in the net (i), and the averaged resistance into delayconversion formula (abnormal delay value) to be applied to the net (i),and NVIA(i,j) and D(i,j) are each of the number of the VIAs included inthe fault j of the net (i) (physical bus reaches the fault j) andaveraged resistance into delay conversion formula (abnormal delay value)to be applied to the fault j.

Here, especially, the NVIA (i,j) requires to pay attention to somepoints in treating the VIAs existing on a plurality of physical paths(described later). As mentioned above, the resistance distribution ofthe VIA resistive defect (resistance defect distribution) f(R) satisfiesthe following expression.

fVIA=∫ _(Rmin) ^(Rmax) f(R)dR

In the fVIA (constant), a VIA is a total occurrence frequency at aresistance section (Rmin≦R≦Rmax) equivalent to the delay fault amongresistive defect by one (approximately equal to occurrence frequency ofresistive defect to be measured in TEG), and it is expected that any VIAbrings the same value under the same process, at least under the samemanufacturing line in the same process. The occurrence frequency of theVIA resistive defects in the entire LSI is NVIA×fVIA (NVIA: the numberof all VIAs inside of LSI). However, a part of the occurrence frequencyappears as the delay faults; an object of the present invention is toobtain the delay faults with high precision. Rmin may be set, forexample, to an averaged value+3×(standard deviation) of a resistancevalue of a normal VIA, and Rmax may be set to a resistance value (e.g.,1 MΩ) which may be presumed as an almost open fault at a value largerthan the resistance value.

On the other hand, also as to an abnormal delay D, a reasonable section(Dmin≦D≦Dmax) is set. In the case that a section is one in which a finedelay fault has a substantial meaning, for example, when a clock periodis 5 ns (200 Hz), Dmin may be set to about 0.1 ns. Dmax may be set to adelay value, by which the abnormal delay D should be treated not as thefine delay fault but as a transition delay fault, for example, to aclock period. Here is a point to notice that Dmin and Dmax are generallydiffer from D(i)(Rmin) and D(i)(Rmax) which are obtained by theresistance into delay conversion formula of each net (i) from Rmin andRmax. The latter satisfies the following relationship together withfVIA, F(i)(D) [the same applies to F(i,j)(D)].

NVIA(i)×fVIA=∫ _(D(i)(Rmin)) ^(D(i)(Rmax)) F(i)(D)dD

On the contrary, a quantity by which an occurrence frequency ofresistive defects of the VIAs on the net (i) develops as (fine) delayfaults is expressed as follows:

∫_(D1) ^(D2)F(i)(D)dD

wherein, D1=max{D(i}(Rmin), Dmin},

D2=min{D(i)(Rmax), Dmax}

The resistance into delay conversion formula expressed with a thick fullline in FIG. 4 shows the fact that both D1 and D2 are decided by Dminand Dmax, respectively, a section (R1 to R2) viewed from the resistanceR satisfies the relationships of Rmin<R1, R2<Rmax, then, the expressionlevel as the delay defects of the VIA resistive defects is substantiallysmaller than NVIA(i)×fVIA. While Rmin and Rmax are especially set toconstants here, they may be set to variables depending on the abnormaldelay D by taking the possibility of an operation by a larger resistancevalue if the load capacitance is smaller (smaller in delay) into account(in this case, fVIA has a slightly different value for each VIA).Strictly speaking, also as to Dmax, a value, in which a minimum value oran averaged value of delays passing through each net or physical path issubtracted from the clock period, may be used.

FIG. 4 collectively shows a flow from the acquisition of the resistancedefect distribution up to obtaining the delay defect distributionaveraged in the nets or faults in the LSI through the resistance intodelay conversion formula at one target layout element. The left part ofFIG. 4 shows the VIA resistive defect distribution f(R) (turned round ata 90 degree angle), the right upper part thereof shows the resistanceinto delay conversion formula of each net (or fault). The FIG. 4 showsthe fact that in the case of the net with a small load capacitance, evenwhen the VIA resistance becomes larger, the (abnormal) delay does notincrease so much; however in the case of the net with a large loadcapacitance, even if the VIA resistance has a small value, a large(abnormal) delay is caused. The FIG. 4 further shows that if the VIAresistance becomes extremely large, an open fault occurs, and if the(abnormal) delay becomes extremely large, a conventional transitiondelay fault occurs. At the right lower part illustrates the averageddelay defect distribution of each of the nets or faults in the LSI.

As described above, the obtaining the resistive physical defectdistribution f(R) of the target layout elements (common to target layoutelements), and the obtaining the resistance into delay conversionformulas of each of the nets or faults including the information of thetarget layout element amount to be added to each delay fault from therelationships among the resistance into delay conversion formulas ofeach target layout element appropriately modeled and each of the VIAsand the nets or inside net physical paths (faults at the tip endsthereof) described in the delay fault-layout element information linkfile make it possible to acquire the delay defect distributions of theindividual nets or faults on the basis of the conversion formulas andthe resistive physical defect distribution f(R) of the target layoutelements. Furthermore, appropriately applying statistic averagingprocesses to the nets, or faults in the LSI enables obtaining the(statistic) delay defect distribution appropriately averaged in theentire LSI so as to be used for calculating the measure of the delayfault test quality of the entire LSI. As for the (statistic) averaging,some calculation expression will be described hereinafter, and anappropriate one may be selected within the range in which a requirementfor, such as an accuracy and execution time is satisfied. Here is apoint of notice that each of the following sums should be produced inthe nets or faults satisfying the prescribed resistances and the delaysections.

Unit to Individual Delay defect be treated data distribution (Averaging)Comment 1) Net f(i) (D)$\sum\limits_{i}\; {{f(i)}\mspace{14mu} (D)\text{/}{n(i)}\text{/}{Nnet}}$The simplest approximation 2) Physicalpath f(i, j) (D)$\sum\limits_{i}\; {\sum\limits_{j}\; {{f\left( {i,j} \right)}\mspace{14mu} (D)\text{/}{Npath}}}$Averaging for wholephysical paths 3) Physicalpath f(i, j) (D)$\sum\limits_{i}\; {\sum\limits_{j}\; {{f\left( {i,j} \right)}\mspace{14mu} (D){\sum\limits_{k}\; {1\text{/}{{m\left( {j,k} \right)}/{Npath}}}}}}$Averaging for whole physical paths(Correct multiplex degree)wherein, n(i): the number of (input) faults included in net (i), Nnet:the total number of nets, Npath: the total number of physical paths(=the number of input faults)

The following will be described the given sums.

1) This sum expresses the simplest averaging, obtains the layout elementinformation by each logical net (i), and uses the sums of delay defectdistributions of each net. However, since the information on branches isnot reflected successfully, it seems appropriate for this sum to be usedfor obtaining an approximate delay defect distribution and forcalculating an approximate delay fault test quality.

2) This sum is the sum of the delay defect distributions of the faultscorresponding to each physical path on the basis of the layoutinformation extracted for each physical path, and it is expected tofurther improve the accuracy more than the sum of 1).

3) This sum obtains the delay defect distributions by taking themultiplex degree of the physical paths into account, and appropriatelydistributes the VIAs shared with other physical paths to each physicalpath by finding the sum of VIAks on the physical paths toward the inputterminal j and 1/m (k) by taking a multiplex degree m(k) into account.Thereby, as a whole, the sum equals to the total number of the VIAs, theinfluence of the VIAs multiply used in a plurality of paths isappropriately included, and it is expected for the delay defectdistribution f(D) matched to the actual status to be obtained. Theforegoing multiplex degree may be easily obtained by counting the timesof appearances of each VIA in the path in each item of net informationof the aforementioned fault-layout information link file.

At last, FIG. 5 shows an execution flow of the first embodiment. In FIG.5, the symbol A indicates an acquisition flow of the physical defectdistributions to be expressed as the abnormality of the resistances orthe currents in the TEG measurement.

On the other hand, in FIG. 5, the symbol B indicates a delayfault-layout element information link, and a flow of layout elementinformation weighting to the delay faults on the basis of the detailedlayout information and the logical net information (corresponding alsoto delay fault information). (However, wherein, it is not necessary todescribe a concrete delay fault test result in the delay fault-layoutelement information link file.) Further, operating appropriate statisticaveraging based on the physical defect distributions and the resistancesinto delay conversion formulas (model formulas) for each net or fault,enables obtaining the delay defect distributions. After this, the flowcalculates the contribution to the delay defect distributions in thenot-detected region of each fault from the Tmgn (i) (delay designinformation) of each fault obtained by the static timing analysis to theLSI and the Tdet (i) of each fault calculated from the result of thedelay fault test by using the delay defect distribution F(D), finds thesum of all faults, then, the flow may obtain the delay fault testquality. More specifically, the flow may calculate in accordance withthe following equations. (The same as that of patent document 1 appliesto this flow. However, the delay defect occurrence [remaining] rate iscalculated. The summing is performed only for the input faults.)

(Delay fault test quality of [input] fault i)

DL(i)=∫_(Tmgn(i)) ^(Tdet(i)) F(D)dD

(Delay fault test quality of whole of LSI)

${{DL}({LSI})} = {\sum\limits_{i}{{DL}(i)}}$

Second Embodiment

Hereinafter, the second embodiment will be described with reference toFIG. 6. The delay defect distribution in the first embodiment obtainsthe distribution of the target layout element amount capable of beingassociated with each delay fault extracted from the LSI and obtains thedelay defect distribution for each net or fault by using the resistanceinto delay conversion formula which has been modeled (simplified) withappropriate accuracy, and obtains the averaged delay defect distributionto be applied to all faults with relative ease by applying (statistic)averaging operations which have been determined as suitable operationsto these delay defect distributions. Based on the obtaining results, thedelay fault test quality to be achieved through the test pattern appliedto the LSI is obtained. However, as mentioned above, there are a varioussteps in the appropriate averaging operation, and to secure necessaryprecision, it is needed to execute the circuit simulations in manycases. Moreover, although, in the first embodiment, the amount of thephysical defect distributions (occurrence distributions) correspondingto the individual faults may be extracted with high precision withrespect to the target layout elements from the layout information of theLSI, the delay fault test quality is calculated once through theaveraging that is the delay defect distribution. The delay defectdistribution before applying the test pattern is obtained, and it is noteasy to employ an appropriate processing (modeling) method for the VIAs,etc., on a plurality of physical paths. In contrast, it is relativelyeasy to calculate the delay fault test quality after applying theconcrete test pattern to the LSI.

Therefore, in the second embodiment, the measure of the delay fault testquality may be directly calculated from a status in which the delaydefect distributions are defined to the individual faults. Actually,since, if the target layout element amount, the physical defectdistribution f(R) and the resistance into delay conversion formulacorresponding to each fault can be defined, the delay defectdistribution f(i)(D) or f(i,j)(D) of each fault i or (i,j) may beobtained, the delay fault test quality of the whole of the LSI may beobtained by calculating the contribution to the measure (defect rate) ofthe delay fault test quality by each fault in the not-detected regionusing the foregoing Tmgn(i) and Tdet(i) and by summing all faults. Thisprocess will be described further specifically with reference to FIG. 7.Now, it is assumed that, as a result of applying a test patternappropriately detecting the delay fault to the LSI, the delay faultassumed at an input terminal j1 of a NAND gate (namely, a delay faultoccurring on a physical path from an output terminal of an AND gate tothe input terminal j1 thereof) and a delay fault assumed at an inputterminal j2 of a buffer (namely, a delay fault occurring on a physicalpath from an output terminal of the AND gate to an input terminal j2thereof) have been detected as slack values S_j1 and S_j2 (S_j1<S_j2),respectively.

In this case, since it is presumed that the interconnect parts whichhave been detected duplicatedly are detected in the smallest slack, theslack values corresponding to the interconnect parts w1, w2, w3 and w4(each indicated with thick full line) become S_j1, S_μl, S_j2 and S_j1,respectively. As to the interconnect part w1, the physical paths up toan input terminal j3 being duplicated, the fault assumed at the inputterminal j3 is not detected yet, and the slack value of interconnectpart except w1 is assumed at least equal to or larger than a testfrequency (>S_j2).

Like this, the delay fault test quality may be obtained directly byobtaining the slack values so as to take a minimum slack in the case ofbeing shared with a plurality of physical paths for each VIAcorresponding to the interconnect parts separately extracted by usingthe fault-layout element information link file, by individuallycalculating the occurrence frequency amounts corresponding to thenot-detected spots on the delay defect distribution by using thephysical defect (resistance) into delay conversion formula correspondingto each VIA through the similar procedure described in the firstembodiment, and by obtaining these slacks values and frequency amountsfor all nets or faults.

Like this, the second embodiment differs from the first embodiment,although there is a need to directly calculate the measure of the delayfault test quality from the status of defining the delay defects to therespective faults, the second embodiment has an advantage that it maydirectly obtain the delay fault test quality corresponding to the testpattern applied to the LSI to achieve the high accuracy without havingto perform a kind of averaging operation to obtain the delay defectdistribution. In the layout element extraction process in FIG. 6, theforegoing delay fault-layout element information link file is output asdelay fault-layout element information link information in a form inwhich concrete slack information is not described, in a process ofweighting the layout element to each fault and a process of calculatingthe delay fault test quality, the concrete slack information isdescribed on the basis of delay design information (static timinganalysis information) and a delay fault ATPG execution result (faultdictionary), and becomes a link file including complete information. Inthis case, the delay fault test quality may be calculated after creatingonce a complete delay fault-layout element information link file;however the delay fault test quality may be directly calculated from theaforementioned delay fault-layout element link information, the delaydesign information and the execution result of the delay fault ATPG.

Third Embodiment

The following will describe the third embodiment by referring to FIG. 8.

By utilizing the delay fault-layout element information link and theweighting method for each fault described in the foregoing embodiment, afault to be preferentially detected becomes clear. Specifically, thethird embodiment preferentially sets objects with heavy weight fromamong the not-detected faults as the object for the generation of thetest pattern. Thereby, it is expected that a test pattern with highdelay fault test quality may be efficiently obtained, and that asmall-sized test pattern may be obtained. In FIG. 8, the calculationapparatus regarding the third embodiment describes the delay designinformation in advance in the delay fault-layout element informationlink information. The calculation of the weight of not-detected faultsmay decrease the execution time by calculating the additional detectionpart of the not-detected part at every generation of additional testpattern after calculating the weight of detected and not-detected faultsof the entire target LSI in a first loop.

Fourth Embodiment

Hereinafter, the fourth embodiment will be described.

While the first, second and third embodiments have been described thedelay fault test quality calculation apparatuses which obtains the delayfault test quality caused by the physical defects of the layout elementsof interconnect of the basic cells, the present invention may beembodied for calculating the delay fault test quality caused by theresistive physical defects of the layout elements inside the basiccells. (Although the content of the fourth embodiment is applicable to amacro cell of a memory, etc., hereinafter simply referred to as a ‘cell’and the macro cell, etc., are included therein.)

A resistive physical defect capable of occurring in a cell includes aresistive open of a minimum-size contact or a minimum VIA in a cell(hereinafter referred to merely a contact or a VIA), a reduction indriving force (increase of on current) of a PMOS/NMOS element, anincrease in off current between a source and drain, and a short-circuitamong interconnects in a cell. Since the whole of the affection ondelays accompanied by these defects appear at an output terminal of eachcell (an input terminal of each net), it is natural that the weights ofrelated layout elements are added to the fault assumed at the outputterminal of the cell [the weight may be added by diving it appropriatelyto the fault to be assumed at an output terminal (input terminal ofcell) of each net]. Since the load capacitance on each defect becomes anentire load capacitance of the connected net, there is no need toextract the detailed position information like the case of the resistivedefect of the VIA at the interconnect among cells in extracting thelayout information. However, since the concrete way of appearance of theabnormal delay accompanied by these defects (any one of dependency onresistance, occurrence frequency, rise/fall, etc.) are all different dueto causes, and acquisition of the resistance into delay conversionformulas suitable for each defects needs a large number of circuitsimulations, the calculation apparatus may extract the spots at whichthe resistive physical defects to be the cause of the delay for eachcell from an actual layout (GDS2), and may respond in turn from theimportant defects by determining from the size and occurrence frequencyof the abnormal delays to be estimated from the physical defectdistribution information acquired from the TEG, etc., an advancesimulation result at a circuit with a defect inserted therein, and anamount (region) of related layout elements (spots). The basic flow fromthe extraction of the resistive defects in the cell up to thecalculation of the delay fault test quality caused by the defects is asfollows (refer to FIG. 9):

1) Extraction of the spots at which the resistive defects possiblyoccurs from an actual layout and determination of the priority(described above).

2) Creation of an abnormal delay library for the principal resistivedefects on the basis of the circuit simulation implementation (normalcircuit and defective circuit) in a cell level.

3) Creation of the delay fault-layout element information link file andextraction of capacitance information on the basis of layout information(DEF) of LSI and of the detected and non-detected information of aresult of applying a test pattern.

4) Calculation of the delay fault test quality of the LSI on the basisof the abnormal delay library of 2) and the capacitance information of3).

The aforementioned 1) and 2) prepare the abnormal delay information ofeach cell as libraries, and one-time created libraries are applicable asthey are to the LSIs using the same library. The abnormal delay libraryof 2) is created by comparing the circuit simulation results between anormal circuit and a circuit with a resistive defect inserted thereinand by extracting the difference of the delays as the abnormal delay,and includes a resistive defect into delay conversion formula and anestimated occurrence frequency to a ‘reference’ load capacitance. As tothe reference load capacitance, generally, a load capacitance rangeconnectable to each cell is approximately decided, and the averaged loadcapacitance may be selected. Depending on the kinds of the defects, thedelay cannot be expressed by a linear expression and the conversionformula cannot be easily modeled sometimes. In such a case, anappropriate conversion formula may be obtained by invoking the MonteCarlo simulation. In 3), the flow calculates the cell to drive each netand the load capacitance for the cell. Since an interconnect length isextracted in the delay fault-layout element information link file shownin the first embodiment, there is a need to calculate the total loadcapacitance from the interconnect length, the name of a connectiondestination cell, etc.; however, the calculation may be obtained at thesame time of the creation of the link file. In the foregoing 2) and 3),to surely activate the defects to be detected and to correctly evaluatethe influences on the delays, it is necessary to acquire the inputinformation to the cell; however the input information is not includedin the delay fault-layout element information link file depicted in thefirst embodiment. Therefore, it is needed to expand the specification soas to describe the input information of the basic cell to drive each netin the same link file, and it is necessary to extract the inputinformation in extracting the layout information. If the flow does notacquire the input information, obtaining a probability of detection onthe basis of the number of combinations of inputs to the cell enablessecuring a certain extent of suitability. In the foregoing 4), the delaydefect distribution at each fault (corresponding to each net) may becalculated on the basis of the main resistive defect into delayconversion formula information and occurrence frequency information atthe reference load capacitance described in the cell abnormal delaylibrary of the 2), and of the load capacitance information at each netof the 3), and may calculate the delay fault test quality caused by thedefect in the cell of the LSI, for example, in the same method of thesecond embodiment. The entire delay fault test quality (defect remainingrate) of the LSI may be obtained by the sum of the delay fault testquality caused by the defects inside the cell and the delay fault testquality caused by the defects among the cells.

Hereinafter, described contents of the abnormal delay library will bedescribed by giving an example of a two-input AND gate (two-input NANDgate+inverter) in FIG. 10. A generic actual layout is not shownspecifically; ‘a white circle’ indicates a contact, ‘a white square’indicates a VIA, and ‘a white triangle’ indicates a power supply (VDD).Among them, since a resistive defect of a contact between a power supply(VDD) and a PMOS source, and a resistive defect of a contact between agrounded point (VSS) and an NMOS source have strong influences on thedelays, they are illustrated as the failures to occur the abnormaldelays. The following format will describe the examples of theseexpressions. The last item of Input expresses the total number ofcombinations capable of being input and the number of combinations to betargeted. The first item of Abnormal Delay represents a signal variationto be affected. Although a delay occurs in charge from the PMOS by aresistive open defect of a contact between PMOS source and power supply(VDD), the delay is output through an inverter, the delay is expressedas Fall. The second item gives the resistive defect into (abnormal)delay conversion formula. For instance, in the expression of“0.90(1c)−0.03(2c)”, the figures in parentheses indicates the order andthe symbol c indicates that the (RC) becomes variables, and the realnumber in front of parentheses indicates a coefficient, then, theexpression represents “D=0.90×(RC)−0.03×(RC)²”. This equation and thecoefficients may be obtained from the difference between the normal celland the circuit simulation result in the cell with the defect insertedtherein. Depending on the case, there is a possibility that it ispreferable to make a variable by R not by (RC), in such a case, only theorder is described in parentheses. The third item represents theconditions of the load capacitance in obtaining the second item(basically, a reference load capacitance is used). If it is hard toexpress in a single equation because the conversion formula iscomplicated, the conversion formula may express the load capacitancerange and a plurality of conversion formulas may be used.

“Distribution of R” expresses the distribution of the defectiveresistances, and it goes along with the similar expression to the seconditem of “Abnormal Delay”.

Format Example “AND2”

# Additional delay by contact PMOS source and VDD resistive open betweenNAND2: Distribution of R: 1.54E−8(−2); Input: A = 0 B = 0¼, A = 0 B = 12/4; Abnormal Delay: Fall 0.90 × (1C) − 0.03 × (2C) 50fF; # Additionaldelay by contact NMOS source and VSS resistive open between NAND2:Distribution of R: 1.54E−8(−2); Input: A = 1 B = 1¼; Abnormal Delay:Rise 1.22 × (1C) 50fF;

As for the increase in on-resistance of the NOMOS and PMOS devices,there is some possibility that the increase therein becomes easier to betreated by using a power supply current (drain-source current) Ids as aparameter rather than by using the on-resistance itself, and aconversion formula using the Ids as a variable may be useful.

According to the foregoing embodiment, since the calculation apparatusobtains the delay defect distribution on the basis of the physicaldefect distribution (using a characteristic resistance value or acurrent value as a variable) of individual circuit and layout elements(their combination) possible to be the cause of the delay fault of thetarget semiconductor integrated circuit (LSI), of the delay fault to bedefined on the logical net (including the input and output terminal ofthe basic cell) to which the circuit and layout elements to be extractedfrom the detailed layout information of the LSI are added as theweights, and of the appropriate resistance-delay conversion model, andobtains the delay fault test quality by means of the test pattern forthe target LSI, or obtains the delay fault test quality without passingthrough the delay defect distribution, it becomes able to obtain themeasure (metric) of the delay fault test quality directly and preciselyassociated with the defect occurrence distribution in the process, whichhas been difficult for the conventional method based on the delay defectdistribution without a clear evidence. For instance, it becomes able todirectly compare the delay fault test quality among different kinds ofproducts on the same manufacturing line by using the defect occurrencerate of the individual layout elements as a parameter, and it becomesable to improve the precision of the delay fault test quality. As aresult, the calculation apparatus can extract the important physicaldefect to efficiently improve the delay fault test quality on the basisof the defect occurrence frequency data of the manufacturing line. Theforegoing embodiment proposes the method for effectively generating thedelay fault test pattern, based on the layout element weight added toeach fault of the individual products. Thereby, a delay fault testpattern with a small size and high quality can be generated.

While the present invention has been described in accordance with someembodiments, the invention is not limited to the specific details andrepresentative embodiments shown and described herein, and in animplementation phase, this invention may be embodied in various formswithout departing from the spirit or scope of the general inventiveconcept thereof.

Each of the foregoing embodiments includes inventions in various phases;the inventions in the various phases can be extracted by appropriatelycombining a plurality of constituent elements disclosed in the foregoingembodiments.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details and representative embodiments shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit or scope of the general inventiveconcept as defined by the appended claims and their equivalents.

1. A delay fault test quality calculation apparatus for calculatingdelay fault test quality to be achieved by a test pattern to be appliedto a semiconductor integrated circuit, comprising: a defect distributionextraction unit which extracts a physical defect distribution ofresistance or current related to layout elements or a combination of thelayout elements composing the semiconductor integrated circuit; a delayfault-layout element information extraction unit which extracts thelayout elements or the combination of the layout elements inside thesemiconductor integrated circuit as delay fault-layout elementinformation by associating the layout elements or the combinationthereof with delay faults to be assumed inside the semiconductorintegrated circuit; a weighting unit which adds weights of the layoutelements or the combination of the layout elements on the basis of thedelay fault-layout element information for each delay fault; and a delayfault test quality calculation unit which calculates the delay faulttest quality on the basis of delay design information of thesemiconductor integrated circuit, detection information of the testpattern to test the semiconductor integrated circuit, executionconditions of the test, the physical defect distribution, and theweights.
 2. The delay fault test quality calculation apparatus accordingto claim 1, wherein the defect distribution extraction unit furtherincludes a delay defect distribution extraction unit which extracts adelay defect distribution on the basis of the physical defectdistribution and the weights added to each of the delay faults; and thedelay fault test quality calculation unit calculates the delay faulttest quality on the basis of delay design information of thesemiconductor integrated circuit, detection information of the testpattern, execution conditions of the test, the physical defectdistribution, and the weights.
 3. The delay fault test qualitycalculation apparatus according to claim 2, wherein the delay defectdistribution extraction unit obtains a delay defect distribution causedby a physical defect distribution of VIAs to each delay fault by using aresistance into delay conversion formula.
 4. The delay fault testquality calculation apparatus according to claim 3, wherein theresistance into delay conversion formula is expressed by an equation asfollows:D(i,k _({j}) ,R)=C(i,k _({j}))×fLOC(i,k _({j}))×R [VIAk on net (i)][{j}=(partial) aggregate of delay faults assumed at a connectiondestination basic cell input terminals of net (i)] wherein, fLOC isdetailed position information of each VIA inside an LSI logical net (i).5. The delay fault test quality calculation apparatus according to claim2, wherein the delay fault test quality calculation unit calculates thedelay fault test quality by an equation expressed as follows:DL(i)=∫_(Tmgn)(i)^(Tdet(i)) F(D)dD [delay fault test quality of (input)fault i] ${{DL}({LSI})} = {\sum\limits_{i}{{DL}(i)}}$ (delay faulttest quality of whole of semiconductor integrated circuit) wherein, F(D)is the delay defect distribution, Tmgn(i) is delay design information ofthe semiconductor integrated circuit, Tdet(i) is detection informationof the test pattern.
 6. The delay fault test quality calculationapparatus according to claim 1, wherein the physical defect distributionis continuously obtained by measuring test element groups for evaluationat shipment tests of products, and by accumulating the measurementresults.
 7. A delay fault test quality calculation method forcalculating delay fault test quality to be achieved by a test pattern tobe applied to a semiconductor integrated circuit, comprising: extractinga physical defect distribution of resistances or currents related tolayout elements or a combination of the layout elements composing thesemiconductor integrated circuit; extracting the layout elements or thecombination of the layout elements inside the semiconductor integratedcircuit as delay fault-layout element information by associating thelayout elements or the combination thereof with delay faults to beassumed inside the semiconductor integrated circuit; adding weights ofthe layout elements or the combination of the layout elements on thebasis of the delay fault-layout element information for each delayfault; and calculating the delay fault test quality on the basis ofdelay design information of the semiconductor integrated circuit,detection information of the test pattern to test the semiconductorintegrated circuit, execution conditions of the test, the physicaldefect distribution, and the weights.
 8. The delay fault test qualitycalculation method according to claim 7, further comprising: extractingthe delay defect distribution on the basis of the physical defectdistribution and the weights added to each of the delay faults; andcalculating the delay fault test quality on the basis of delay designinformation of the semiconductor integrated circuit, detectioninformation of the test pattern, execution conditions of the test, thephysical defect distribution, and the weights.
 9. The delay fault testquality calculation method, according to claim 8, wherein the extractingof the delay defect distribution obtains a delay defect distributioncaused by physical defect distributions of VIAs to each delay fault byusing a resistance into delay conversion formula.
 10. The delay faulttest quality calculation method according to claim 9, wherein theresistance into delay conversion formula is expressed in an equation asfollows:D(i,k _({j}) ,R)=C(i,k _({j}))×fLOC(i,k _({j}))×R (VIAk on net (i))[{j}=(partial) aggregate of delay faults assumed at a connectiondestination basic cell input terminals of net (i)] wherein, fLOC isdetailed position information of each VIA inside an LSI logical net (i).11. The delay fault test quality calculation method according to claim8, wherein the calculating of the delay fault test quality calculatesthe delay fault test quality by an equation expressed as follows:DL(i)=∫_(Tmgn(i)) ^(Tdet(i)) F(D)dD [delay fault test quality of (input)fault i] ${{DL}({LSI})} = {\sum\limits_{i}{{DL}(i)}}$ (delay faulttest quality of whole of semiconductor integrated circuit) wherein, F(D)is the delay defect distribution, Tmgn(i) is delay design information ofthe semiconductor integrated circuit, Tdet(i) is detection informationof the test pattern.
 12. The delay fault test quality calculation methodaccording to claim 7, wherein the physical defect distribution iscontinuously obtained by measuring test element groups for evaluation atshipment tests of products, and by accumulating the measurement results.13. A delay fault test pattern generation apparatus for generating adelay fault test pattern, comprising: a defect distribution extractionunit which extracts a physical defect distribution of resistances orcurrents related to layout elements or a combination of the layoutelements composing the semiconductor integrated circuit; a delayfault-layout element information extraction unit which extracts thelayout elements or the combination of the layout elements inside thesemiconductor integrated circuit as delay fault-layout elementinformation by associating the layout elements or the combinationthereof with delay faults to be assumed inside the semiconductorintegrated circuit; a weighting unit which adds weights of the layoutelements or the combination of the layout elements on the basis of thedelay fault-layout element information for each delay fault; a testpattern generation unit which preferentially generates a test patternfor non-detected faults with heavy weights on the basis of weights offaults to which the weights are added by the weighting unit; and a delayfault test quality calculation unit which calculates the delay faulttest quality on the basis of delay design information of thesemiconductor integrated circuit, detection information of the testpattern to test the semiconductor integrated circuit, executionconditions of the test, the physical defect distribution, and theweights.
 14. The delay fault test pattern generation apparatus accordingto claim 13, wherein the defect distribution extraction unit furtherincludes a delay defect distribution extraction unit which extracts adelay defect distribution on the basis of the physical defectdistribution and the weights added to each of the delay faults; and thedelay fault test quality calculation unit calculates the delay faulttest quality on the basis of delay design information of thesemiconductor integrated circuit, detection information of the testpattern, execution conditions of the test, the physical defectdistribution, and the weights.
 15. The delay fault test patterngeneration apparatus according to claim 14, wherein the delay defectdistribution extraction unit obtains a delay defect distribution causedby a physical defect distribution of VIAs to each delay fault by using aresistance into delay conversion formula.
 16. The delay fault testpattern generation apparatus according to claim 15, wherein theresistance into delay conversion formula is expressed by an equation asfollows:D(i,k _({j}) ,R)=C(i,k _({j}))×fLOC(i,k _({j}))×R [VIAk on net (i)][{j}=(partial) aggregate of delay faults assumed at a connectiondestination basic cell input terminals of net (i)] wherein, fLOC isdetailed position information of each VIA inside an LSI logical net (i).17. The delay fault test pattern generation apparatus according to claim14, wherein the delay fault test quality calculation unit calculates thedelay fault test quality by an equation expressed as follows:DL(i)=∫_(Tmgn(i)) ^(Tdet(i)) F(D)dD [delay fault test quality of (input)fault i] ${{DL}({LSI})} = {\sum\limits_{i}{{DL}(i)}}$ (delay faulttest quality of whole of semiconductor integrated circuit) wherein, F(D)is the delay defect distribution, Tmgn(i) is delay design information ofthe semiconductor integrated circuit, Tdet(i) is detection informationof the test pattern.
 18. The delay fault test pattern generationapparatus according to claim 13, wherein the physical defectdistribution is continuously obtained by measuring test element groupsfor evaluation at shipment tests of products, and by accumulating themeasurement results.